Opening for undergraduate students
Author
comsys
Date
2017-01-05 09:47
Views
1497
Computer Systems & Reliable SOC Lab is recruiting students for internship.
Founded in 1994, our lab has been carrying out a diverse array of research projects in the areas of VLSI design, DFT, and CAD in order to implement high performance, high reliability systems in VLSI/CAD.
The primary focus of our research is high reliability SoC (System On a Chip) implementation.
1. Research Area
(1) SOC Design
1) Chip design for computing and media
2) Chip design for network and communication
3) Chip design for test equipments
(2) Test
1) DFT (design for testability) : Scan, LBIST, ABIST, JTAG, etc.
2) SOC test methodology : P1500, Compression low power test, DFM, etc.
3) Memory test : MBIST, BIRA, RA, etc.
(3) CAD
1) Design verification and simulation
2) ATPG (automatic test pattern generation) and fault simulation
3) Systhesis
For more information, please refer to the “Projects” section of this website.
2. Notes on Recruitment
(1) Any student who is interested in the above research topic and has a desire to gain in-depth knowledge in the topic may apply
(2) Application requirement : Must be an undergraduate student in the third or fourth year who is interested in SOC
(3) Research support : Funding provided
3. Application and contact
(1) Required document: Resume (Any form is acceptable)
(2) How to : Please visit Computer Systems & Reliable SOC Lab (room 631 in the third engineering
building / Yonsei university) or email your application to Professor Kang.
(shkang@yonsei.ac.kr / 2123-2775)
Founded in 1994, our lab has been carrying out a diverse array of research projects in the areas of VLSI design, DFT, and CAD in order to implement high performance, high reliability systems in VLSI/CAD.
The primary focus of our research is high reliability SoC (System On a Chip) implementation.
1. Research Area
(1) SOC Design
1) Chip design for computing and media
2) Chip design for network and communication
3) Chip design for test equipments
(2) Test
1) DFT (design for testability) : Scan, LBIST, ABIST, JTAG, etc.
2) SOC test methodology : P1500, Compression low power test, DFM, etc.
3) Memory test : MBIST, BIRA, RA, etc.
(3) CAD
1) Design verification and simulation
2) ATPG (automatic test pattern generation) and fault simulation
3) Systhesis
For more information, please refer to the “Projects” section of this website.
2. Notes on Recruitment
(1) Any student who is interested in the above research topic and has a desire to gain in-depth knowledge in the topic may apply
(2) Application requirement : Must be an undergraduate student in the third or fourth year who is interested in SOC
(3) Research support : Funding provided
3. Application and contact
(1) Required document: Resume (Any form is acceptable)
(2) How to : Please visit Computer Systems & Reliable SOC Lab (room 631 in the third engineering
building / Yonsei university) or email your application to Professor Kang.
(shkang@yonsei.ac.kr / 2123-2775)