2019년 12월 26일 강일권 Software Engineer 님 세미나 안내

Author
comsys
Date
2019-12-26 11:02
Views
81
2019년 12월 26일 본 연구실을 졸업하신 강일권 선배님의 세미나가 진행됩니다.

 개최일시 : 2019년 12월 26일 목요일 14시 30분~15시 30분
 개최장소 : 제3공학관 C616호
 세미나 제목 : Digital IC Layout Design Automation for Advanced Technology Nodes - Global Placement, Routability Analysis, and 3-D IC Floorplan Representation
 발표초록 : While "Moore's Law" and "Dennard Scaling" have shown the correction of slowing-down, industry-leading foundries are relentlessly continuing to develop sub-5nm technologies. IC industry requires even more sophisticated design methodologies to overcome nontrivial/complicated challenges. IC layout design directly impacts on timing closure, die utilization, routability, and design turnaround time (TAT); these in turn affect the classic design metrics of operating frequency, yield, power consumption and cost. In this talk, Dr. Kang briefly describes the fundamental physical design flow, then presents new IC design automation techniques in the highlight of (1) the state-of-the-art global placement algorithm, (2) SAT- (satisfiability-) based design rule-correct routability analysis and diagnosis, and (3) 3-D IC floorplan representation method.

 강연자 성함&직함 / 소속 : 강일권 Software Engineer / Cadence Design Systems
 초청자 : 전기전자공학과 교수 강성호