주 교재 : |
Logic Synthesis
by S. Devadas, A. Ghosh and
K. Keutzer |
참고 서적 : |
Design and analysis of computer algorithm
by
Aho, Hopcroft and Ullman
Synthesis and Optimization of
digital circuit
by G. Micheli |
주요 주제 : |
효과적인 알고리듬 설계
2 level 조합
회로
2 level 회로 합성
2 level 회로 테스트 용의성 |
Multi level 조합 회로
Multi level 회로의 합성
Multi level 회로의 딜레이
Multi level 회로의 테스트 용의도 |
학점 평가 : |
기말 고사
중간 고사
프로젝트
과제 |
30%
30%
20%
20% |
자료 : |
수업계획서
Binary
decision diagrams
Boolean
algebra
Formal
verification
Heuristic
minimization of two level circuits
Introduction
Models
of sequential systems
Multi-level
logic synthesis
Multi-level
minimization
Quick
tour of logic synthesis
Synthesis
and verification of finite state machines
Hardware
acceleration
Logic
emulation
Design
error simulation
Logic
simulation
Timing
verification
Synthesis
of two level circuits
Hardware/Software
Co-design / Co-verification
System
level verification issues
Verification/Hardware
acceleration
|