32 |
"A New Weight Set Generation Algorithm for Weighted Random Pattern Generation"
|
31 |
"New Scan Design of Asynchronous Sequential Circuits"
|
30 |
"At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks"
|
29 |
"Weight Set Optimization for Weighted Random Pattern Generation"
|
28 |
"A Split Walking One Sequence for Wiring Interconnections"
|
27 |
"A New BIST for Diagnosis and Transparent Testing in High Density SRAMs"
|
26 |
"An Efficient Bist Architecture for Boards with Multiple Scan Chains"
|
25 |
"A Memory Based Pipelined Architecture for Blocking Effect Removal in HDTV"
|
24 |
"Built-In Self Test for High Density SRAMs"
|
23 |
"Built-In Self Test for Content Addressable Memories"
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