Textbook : |
Logic Synthesis
by S. Devadas, A. Ghosh and K. Keutzer |
References : |
The Design and Analysis of computer Algorithms
by Aho, Hopcroft and Ullman
Synthesis and Optimization of digital Circuits
by G. Micheli |
Main Topics : |
Design of Efficient Algorithm
2 Level Combinational Circuits
Synthesis of 2 Level Circuits
Testability of 2 Level Circuits |
Multilevel Combinational Circuits
Synthesis of Multilevel Circuits
Delay of Multilevel Circuits
Testability of Multilevel Circuits |
Grading : |
Final
Midterm
Project
Homeworks |
30%
30%
20%
20% |
Materials : |
Indexing
Binary
decision diagrams
Boolean
algebra
Formal
verification
Heuristic
minimization of two level circuits
Introduction
Models
of sequential systems
Multi-level
logic synthesis
Multi-level
minimization
Quick
tour of logic synthesis
Synthesis
and verification of finite state machines
Hardware
acceleration
Logic
emulation
Design
error simulation
Logic
simulation
Timing
verification
Synthesis
of two level circuits
Hardware/Software
Co-design / Co-verification
System
level verification issues
Verification/Hardware
acceleration |