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64 |
"An Efficient Processor Architecture for Digital Signal Processing using Registered Logic"
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63 |
"Efficient Test Data Compression Using Transition Directed Run-length Code in System-on-a-Chip"
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62 |
"Layout-aware Low Power Test Pattern Generation"
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61 |
"An Efficient Test Scheduling Algorithm in Networks on Chip Architecture"
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60 |
"An Immunotronic Approach for Hardware Fault Detection and its Application to the Design of Stigmergy Engine"
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59 |
"Efficient Test Point Selection using Multi-Objective Genetic Algorithms with Biological Kronecker Delta Evolution"
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58 |
"An Effective Metric for System Survivability"
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57 |
"Deterministic BIST Based on a Clustered Reconfigurable Interconnection Network"
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56 |
"RAIN : RAndom INsertion Scheduling Algorithm for SoC Test"
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