IEEE T VLSI 논문게재 예정 - 신효영 외

Author
comsys
Date
2014-09-04 16:14
Views
662
IEEE Transactions on Very Large Scale Integration Systems에 논문게재 예정 되었습니다.

제목: An Interleaving Test Algorithm for Sub-threshold Leakage Current Defects in DRAM Considering the Equal Bit Line Stress

축하드립니다~^^