26 |
"REDUDANCY ANALYSIS METHOD AND REDUDANCY ANALYSIS APPARATUS"
|
25 |
"ON-CHIP SECURITY CIRCUIT FOR DETECTING AND PROTECTING AGAINST INVASIVE ATTACKS"
|
24 |
"METHOD AND APPARATUS FOR BUILT IN REDUNDANCY ANALYSIS WITH DYNAMIC FAULT RECONFIGURATION"
|
23 |
"STACKED MEMORY APPARATUS USING ERROR CORRECTION CODE AND REPAIR METHOD THEREOF"
|
22 |
"STACKED MEMORY DEVICE USING BASE DIE SPARE CELL AND METHOD OF REPAIRING THE SAME"
|
21 |
"THREE DIMENTIONAL INTEGRATED CIRCUIT HAVING REDUNDANT THROUGH SILICON VIA BASED ON ROTATABLE CUBE"
|
20 |
"CIRCUIT FOR TESTING AND ANALYZING TSV AND METHOD OF TESTING THE SAME"
|
19 |
"THREE-DIMENSIONAL INTEGRATED CIRCUIT"
|
18 |
"TEST CIRCUIT FOR 3D SEMICONDUCTOR DEVICE AND METHOD FOR TESTING THEREOF"
|
17 |
"SEMICONDUCTOR DEVICE AND METHOD FOR TESTING THE SAME"
|
[1][2][3][4] |