168 |
"A Selective Error Data Capture Method using On-Chip DRAM for Silicon Debug of Multi-core Design"
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167 |
"Test Data Reduction Method Based on Berlekamp-Massey Algorithm"
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166 |
"LARECD : Low Area overhead and Reliable Error Correction DMR architecture"
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165 |
"Test Item Priority Estimation for High Parallel Test Efficiency under ATE Debug Time Constraints"
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164 |
"Broadcast Scan Compression Based on Deterministic Pattern Generation Algorithm"
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163 |
"Off-Chip Test Architecture for Improving Multi-Site Testing Efficiency using Tri-State Decoder and 3V-Level Encoder"
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162 |
"Test Access Mechanism for Stack Test Time Reduction of 3-Dimensional Integrated Circuit"
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161 |
"A New Online Test and Debug Methodology for Automotive Camera Image Processing System"
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160 |
"A TSV Test Structure for Simultaneously Detecting Resistive Open and Bridge Defects in 3D-ICs"
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159 |
"P-Backtrace A New Scan Chain Diagnosis Method with Probability"
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