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177 |
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176 |
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175 |
"Low Power Scan Chain Architecture Based on Circuit Topology"
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174 |
"A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain"
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173 |
"Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test"
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172 |
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171 |
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170 |
"A New Repair Scheme for TSV-based 3D Memory using Base Die Repair Cells"
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169 |
"An Efficient Built-in Self-Repair Scheme for Area Reduction"
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