175

"Low Power Scan Chain Architecture Based on Circuit Topology"
Heetae Kim, Hyunggoy Oh, Sangjun Lee, and Sungho Kang
International SOC Design Conference ( ISOCC 2018 )
NOV 2018

174

"A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain"
HyeonChan Lim, Seokjun Jang, and Sungho Kang
International SOC Design Conference ( ISOCC 2018 )
NOV 2018

173

"Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test"
Hyunggoy Oh, Heetae Kim, Sangjun Lee, and Sungho Kang
International SOC Design Conference ( ISOCC 2018 )
NOV 2018

172

"3D Memory Formed of Unrepairable Memory Dice and Spare Layer"
Donghyun Han, Hayoung Lee, Seungtaek Lee, Minho Moon, and Sungho Kang
TENCON 2018
Oct 2018

171

"Neural Network Reliability Enhancement Approach using Dropout Underutilization in GPU"
Dongsu Lee, Hyunyul Lim, Taehyun Kim, and Sungho Kang
TENCON 2018
Oct 2018

170

"A New Repair Scheme for TSV-based 3D Memory using Base Die Repair Cells"
Donghyun Han, Hayoung Lee, Donghyun Kim, and Sungho Kang
International SOC Design Conference (ISOCC 2017)
September 2017

169

"An Efficient Built-in Self-Repair Scheme for Area Reduction"
Keewon Cho, Young-woo Lee, Sungyoul Seo, and Sungho Kang
International SOC Design Conference (ISOCC 2017)
September 2017

168

"A Selective Error Data Capture Method using On-Chip DRAM for Silicon Debug of Multi-core Design"
Hyunggoy Oh, Heetae Kim, Jaeil Lim, and Sungho Kang
International SOC Design Conference (ISOCC 2017)
September 2017

167

"Test Data Reduction Method Based on Berlekamp-Massey Algorithm"
HyeonChan Lim, Junghwan Kim, Soyeon Kang, and Sungho Kang
International SOC Design Conference (ISOCC 2017)
September 2017

166

"LARECD : Low Area overhead and Reliable Error Correction DMR architecture"
Hyunyul Lim, Taehyun Kim, Dongsu Lee, and Sungho Kang
International SOC Design Conference (ISOCC 2017)
September 2017


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