8

"Automatic VHDL Model Generation System"
Sungho Kang, Stephen A. Szygenda
Proceedings of Conference on Hardware Description Languages and Their Application
pp.339-346, April 1993

7

"Modeling and Simulation of Design Errors"
Sungho Kang, Stephen A. Szygenda
Proceedings of IEEE International Conference on Computer Design
pp 443-446, October 1992

6

"New Design Error Modeling and Design Validation Metrics"
Sungho Kang, Stephen A. Szygenda
Proceedings of European Design Automation Conference
pp.472-477, September 1992

5

"Automatic Error Pattern Generation for Design Error Detection in a Design Validation"
Sungho Kang, Stephen A. Szygenda
Proceedings of IEEE International ASIC Conference
pp.533-536, September 1992

4

"Fast Logic Simulation For Design Verification, using a Non-Dominating Value 'S'"
Sungho Kang, Stephen A. Szygenda
Proceedings of 25th Summer Simulation Conference
pp.235-239, July 1992

3

"Comparative Analysis of Error Simulation Algorithms for Design Validation"
Sungho Kang, Stephen A. Szygenda
Proceedings of Modeling and Simulation Conference
pp.2553-2564, May 1992

2

"AFMG: Automatic Functional Model Generation System for Digital Logic Simulation"
Changho Han, Sungho Kang, Stephen A. Szygenda
Proceedings of IEEE International ASIC Conference
pp.12-2.1 - 12-2.4, September, 1991

1

"MOVE: Model Verification System"
Sungho Kang, Stephen A. Szygenda
Proceedings of IEEE International Conference on Computers and Communications
pp.762-768, March 1991