18 |
"Sampling Based Design Verification Using Design Error Models"
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17 |
"An Efficient Method of Path-Delay Test Generation For Standard Scan Designs"
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16 |
"Single Chip Array Processor for High Performance Design Error Simulation"
|
15 |
"A New Design Error Simulation Tool based on Error Model and Sampling Techniques"
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14 |
"Automatic Code Generation for Simulators using Domain Specific Automatic Programming Techniques"
|
13 |
"Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation"
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12 |
"High Performance Fault Simulation using a new Hardware Accelerator"
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11 |
"Path-Delay Fault Simulation for a Standard Scan Design Methodology"
|
10 |
"Fastpath: A Path-Delay Test Generator for Standard Scan Design Methodology"
|
9 |
"A Path-Delay Test Generator for Large VLSI Circuits"
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