|
198 |
"Pair-Grouping Scan Chain Architecture for Multiple Scan Cell Fault Diagnosis"
|
|
197 |
"Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST"
|
|
196 |
"FAME: Fault Address Memory Structure for Repair Time Reduction"
|
|
195 |
"A Circular-based TSV Repair Architecture"
|
|
194 |
"Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC"
|
|
193 |
"Hybrid Test Access Mechanism for Multiple Identical Cores"
|
|
192 |
"Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure"
|
|
191 |
"Secure Scan Design through Pseudo Fault Injection"
|
|
190 |
"An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA"
|
|
189 |
"Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory"
|
| [1][2][3][4][5][6][7][8][9][10] Next Page>> |