38 |
"A 0.35um CMOS low noise VGA"
|
37 |
"Test Methodology for Low Power SRAMs"
|
36 |
"Testability Strategy and DFT Methodology of CalmRISC32"
|
35 |
"Delay Test for System on Chip"
|
34 |
"Dynamic Power Supply Current Test for CMOS SRAMs"
|
33 |
"An Efficient Interconnect Test Using BIST Module in a Boundary Scan Environment"
|
32 |
"A New Weight Set Generation Algorithm for Weighted Random Pattern Generation"
|
31 |
"New Scan Design of Asynchronous Sequential Circuits"
|
30 |
"At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks"
|
29 |
"Weight Set Optimization for Weighted Random Pattern Generation"
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