68 |
"An Optimal Diagnosis Algorithm for Dual-Port Memories"
|
67 |
"A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture"
|
66 |
"A Nested Loop-Level Parallelism for DSP in Reconfigurable Computing using Forward Scheduling"
|
65 |
"A New Hardware Efficient Interconnect BIST"
|
64 |
"An Efficient Processor Architecture for Digital Signal Processing using Registered Logic"
|
63 |
"Efficient Test Data Compression Using Transition Directed Run-length Code in System-on-a-Chip"
|
62 |
"Layout-aware Low Power Test Pattern Generation"
|
61 |
"An Efficient Test Scheduling Algorithm in Networks on Chip Architecture"
|
60 |
"An Immunotronic Approach for Hardware Fault Detection and its Application to the Design of Stigmergy Engine"
|
59 |
"Efficient Test Point Selection using Multi-Objective Genetic Algorithms with Biological Kronecker Delta Evolution"
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