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98 |
"A Prevenient Voltage Stress Test Method for High Density Memory"
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97 |
"A New Low Energy BIST Using A Statistical Code"
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96 |
"SA-Based Test Time Optimization for SoCs Using Networks-on-Chip"
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95 |
"A New LFSR Reseeding based Test Compression Scheme by Virtual Reduction of Smax"
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94 |
"Power-Aware Task Scheduling for Dynamic Voltage Selection and Power Management for Multiprocessors"
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93 |
"An Efficient BIST Architecture for Embedded Dual-Port Memories"
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92 |
"A Compilation System Development for Regular Reconfigurable Architecture using Abstract Graph Model"
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91 |
"An Improved False Aggressor Pruning Algorithm for an Effective Crosstalk Test"
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90 |
"An Efficient BIST (Built-in Self-test) for A/D converters"
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89 |
"A New Low Power BIST Architecture Based on Probability Models"
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