195 |
"A Circular-based TSV Repair Architecture"
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194 |
"Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC"
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193 |
"Hybrid Test Access Mechanism for Multiple Identical Cores"
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192 |
"Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure"
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191 |
"Secure Scan Design through Pseudo Fault Injection"
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190 |
"An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA"
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189 |
"Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory"
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188 |
"Fail Memory Configuration Set for RA Estimation"
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187 |
"Diagnosis of Scan Chain Faults Based-on Machine-Learning"
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186 |
"Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair "
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