22 |
"Efficient Redundancy Identification for Test Pattern Generation"
|
21 |
"A Parallel Test Algorithm for Pattern Sensitive Faults in Semionductor Random Access Memories"
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20 |
"Efficient Simulation Model Generation Using Automatic Programming Techniques"
|
19 |
"An Efficient Path-Delay Fault Simulator for Mixed Level Circuits"
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18 |
"Sampling Based Design Verification Using Design Error Models"
|
17 |
"An Efficient Method of Path-Delay Test Generation For Standard Scan Designs"
|
16 |
"Single Chip Array Processor for High Performance Design Error Simulation"
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15 |
"A New Design Error Simulation Tool based on Error Model and Sampling Techniques"
|
14 |
"Automatic Code Generation for Simulators using Domain Specific Automatic Programming Techniques"
|
13 |
"Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation"
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