72 |
"A Delay Testing Considering Sub-Aggressor Effects"
|
71 |
"A New BIST Architecture for Word Oriented Memory"
|
70 |
"Accelerated Multi-phase Packet Classification Architecture Using Internal Buffer"
|
69 |
"A Functional Pattern Generation Method For Faulty Scan Chain Diagnosis"
|
68 |
"An Optimal Diagnosis Algorithm for Dual-Port Memories"
|
67 |
"A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture"
|
66 |
"A Nested Loop-Level Parallelism for DSP in Reconfigurable Computing using Forward Scheduling"
|
65 |
"A New Hardware Efficient Interconnect BIST"
|
64 |
"An Efficient Processor Architecture for Digital Signal Processing using Registered Logic"
|
63 |
"Efficient Test Data Compression Using Transition Directed Run-length Code in System-on-a-Chip"
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