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"3D Memory Formed of Unrepairable Memory Dice and Spare Layer"
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171 |
"Neural Network Reliability Enhancement Approach using Dropout Underutilization in GPU"
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170 |
"A New Repair Scheme for TSV-based 3D Memory using Base Die Repair Cells"
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169 |
"An Efficient Built-in Self-Repair Scheme for Area Reduction"
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168 |
"A Selective Error Data Capture Method using On-Chip DRAM for Silicon Debug of Multi-core Design"
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167 |
"Test Data Reduction Method Based on Berlekamp-Massey Algorithm"
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166 |
"LARECD : Low Area overhead and Reliable Error Correction DMR architecture"
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165 |
"Test Item Priority Estimation for High Parallel Test Efficiency under ATE Debug Time Constraints"
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164 |
"Broadcast Scan Compression Based on Deterministic Pattern Generation Algorithm"
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163 |
"Off-Chip Test Architecture for Improving Multi-Site Testing Efficiency using Tri-State Decoder and 3V-Level Encoder"
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