202 |
"Logic Diagnosis Based on Deep Learning for Multiple Faults"
|
201 |
"Cell-Aware Scan Diagnosis Using Partially Synchronous Set and Reset"
|
200 |
"An Improved Early Termination Methodology Using Convolutional Neural Network"
|
199 |
"PROG: Per-Row Output Generator for BOST"
|
198 |
"Pair-Grouping Scan Chain Architecture for Multiple Scan Cell Fault Diagnosis"
|
197 |
"Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST"
|
196 |
"FAME: Fault Address Memory Structure for Repair Time Reduction"
|
195 |
"A Circular-based TSV Repair Architecture"
|
194 |
"Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC"
|
193 |
"Hybrid Test Access Mechanism for Multiple Identical Cores"
|
[1][2][3][4][5][6][7][8][9][10] Next Page>> |