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24 |
"Built-In Self Test for High Density SRAMs"
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23 |
"Built-In Self Test for Content Addressable Memories"
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22 |
"Efficient Redundancy Identification for Test Pattern Generation"
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21 |
"A Parallel Test Algorithm for Pattern Sensitive Faults in Semionductor Random Access Memories"
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20 |
"Efficient Simulation Model Generation Using Automatic Programming Techniques"
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19 |
"An Efficient Path-Delay Fault Simulator for Mixed Level Circuits"
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18 |
"Sampling Based Design Verification Using Design Error Models"
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17 |
"An Efficient Method of Path-Delay Test Generation For Standard Scan Designs"
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16 |
"Single Chip Array Processor for High Performance Design Error Simulation"
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