"Grouping-based TSV Test Architecture for Resistive Open and Bridge Defects in 3D-ICs"
Young-woo Lee, Hyeonchan Lim, and Sungho Kang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
vol.36, no.10, pp.1759-1763, October 2017


"DRAM-based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores"
Hyunggoy Oh, Inhyuk Choi, Sungho Kang
IEEE Transactions on Computers
vol.66, no.9, pp.1504-1517, September 2017


"DVFS-aware refresh management for 3D DRAM over processor architecture "
Jaeil Lim, Heetae Kim, Hyunggoy Oh, Sungho Kang
IET Electronics Letters
vol.53,no.14, pp.910-912, July 2017


"Reconfigurable scan architecture for Test Power and Data Volume Reduction"
Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang
IEICE Electronics Express (ELEX)
vol.14, no.13, pp.1-7, July 2017


"Proof of Concept of Home IoT Connected Vehicles"
Younsun Kim, Hyunggyo Oh, Sungho Kang
vol.17, no.6, pp.1289:1-1289:13., June 2017


"R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies"
Jaeseok Park, Minho Cheong, Sungho Kang
IEEE Transactions on Reliability
vol.66, no.2, pp.458-466, June 2017


"Chain-based Approach for Fast Through-Silicon-Via Coupling Delay Estimation"
Jaewon Jang, Minho Cheong, Jin-Ho Ahn, Sung Kyu Lim, Sungho Kang
IEEE Transactions on Very Large Scale Integration Systems
vol.25, no.3, pp.1178-1182, March 2017


"Hardware-Efficient Built-in Redundancy Analysis for Memory with Various Spares"
Jooyoung Kim, Woosung Lee, Keewon Cho, and Sungho Kang
IEEE Transactions on Very Large Scale Integration Systems
vol.25, no.3, pp.844-856, March 2017


"Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory"
Jaewon Cha, Keewon Cho, Seunggeon Yu, Sungho Kang
Journal of Semiconductor Technology and Science (JSTS)
vol.17, no.1, pp.147-155, February 2017


"A Low-cost DAC BIST Structure using a Resistor Loop"
Jaewon Jang, Heetae Kim, Sungho Kang
PLoS One
vol.12, no.2, e0172331, February 2017

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