|
180 |
"Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks"
|
|
179 |
"Reconfigurable Scan Architecture for High Diagnostic Resolution"
|
|
178 |
"A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs"
|
|
177 |
"A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-based Lock and Key"
|
|
176 |
"Enhanced Post-bond Test Architecture for Bridge Defects Between the TSVs"
|
|
175 |
"Effective Spare Line Allocation Built-in Redundancy Analysis with Base Common Spare for Yield Improvement of 3D Memory"
|
|
174 |
"On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug"
|
|
173 |
"An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process"
|
|
172 |
"A New Logic Topology-based Scan Chain Stitching for Test-Power Reduction"
|
|
171 |
"Prediction based Error Correction for GPU Reliability with Low Overhead"
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|
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