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9	"An Efficient Pipelined Parallel Architecture for Blocking Effect Removal in HDTV" Jae-Wook Lee, Myung-Hoon Yang, Sungho Kang, Yoonsik Choe IEEE Transactons on Consumer Electronics vol. 43, no. 2, pp 149-156, May 1997
8	"Knowledge Based Automatic Model Generation System" Sungho Kang IEE Proceedings of Circuits, Devices and Systems vol. 144, no. 2, pp 88-96, April 1997
7	"High Performance Hardware Accelerator for Design Error Simulation" Sungho Kang IEE Proceedings of Circuits, Devices and Systems vol. 144, no. 2, pp 81-87, April 1997
6	"Parallel BIST Architecture for CAMs" Yong Seok Kang, Jong Cheol Lee, Sungho Kang IEE Electronics Letters vol. 33, no. 1, pp 30-31, January 1997
5	"A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture" Sungho Kang, Youngmin Hur, Stephen A. Szygenda VLSI Design Gorden and Breach Science Publishers vol. 4, no. 2, pp 119-133, April 1996
4	"Automatic Simulator Generation System" Sungho Kang, Stephen A. Szygenda SCS Simulation vol. 63, no. 6, pp 360-368, December 1994
3	"Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling" Sungho Kang, Stephen A. Szygenda IEEE Design and Test of Computers vol. 11, no. 1, pp 18-26, March 1994
2	"The Simulation for Automation System(SAS): Concepts, Implementation, and Results" Sungho Kang, Stephen A. Szygenda IEEE Transactions on VLSI Systems vol. 2, no. 1, pp 89-99, March 1994
1	"Development of a Reduced Time Interval Partitioned Simulation Algorithm" Sungho Kang, Stephen A. Szygenda IEE Computer Aided Design vol. 21, no. 1, pp 25-32, January 1989

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