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14	"Efficient Test Generation Using Redundancy Identification" Sangyun Han, Sungho Kang IEICE Letters vol. E83-D,no 9, pp1813-1815 , September 2000
13	"Efficient Test Generation Algorithm for Path Delay Faults" Myung-Gyun Kim, Sungho Kang IEE Electronics Letters vol. 36, no. 1, pp 13-14, January 2000
12	"Efficient Algorithm and Architecture for Scan Conversion in HDTV" Myung-Hoon Yang, Jae-Wook Lee, Sungho Kang IEE Proceedings of Computer and Digital Techniques vol. 145, no. 4, pp 287-291, June 1998
11	"Efficient Algorithm and Architecture for Post-processor in HDTV" Jae-Wook Lee, Jeong-Woo Park, Myung-Hoon Yang, Sungho Kang, Yoonsik Choe IEEE Trans. on Consumer Electronics vol. , no. 4, pp 16-26, February 1998
10	"Simulatior Path Delay Faults on Mixed Level Circuits" Yong Tae Yim, Yong Seok Kang, Sungho Kang IEE Proceedings of Circuits, Devices and Systems vol. 144, no. 4, pp 236-242, August 1997
9	"An Efficient Pipelined Parallel Architecture for Blocking Effect Removal in HDTV" Jae-Wook Lee, Myung-Hoon Yang, Sungho Kang, Yoonsik Choe IEEE Transactons on Consumer Electronics vol. 43, no. 2, pp 149-156, May 1997
8	"Knowledge Based Automatic Model Generation System" Sungho Kang IEE Proceedings of Circuits, Devices and Systems vol. 144, no. 2, pp 88-96, April 1997
7	"High Performance Hardware Accelerator for Design Error Simulation" Sungho Kang IEE Proceedings of Circuits, Devices and Systems vol. 144, no. 2, pp 81-87, April 1997
6	"Parallel BIST Architecture for CAMs" Yong Seok Kang, Jong Cheol Lee, Sungho Kang IEE Electronics Letters vol. 33, no. 1, pp 30-31, January 1997
5	"A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture" Sungho Kang, Youngmin Hur, Stephen A. Szygenda VLSI Design Gorden and Breach Science Publishers vol. 4, no. 2, pp 119-133, April 1996

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