39 |
"A New Low Power Test Pattern Generator for BIST Architecture"
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38 |
"An Efficient Parallel Architecture Using Register-in-Logic Element for Digital Signal Processing"
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37 |
"An Effective Built-In Self-Test for Chargepump PLL"
|
36 |
"An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications"
|
35 |
"Code-Width Testing Based Compact ADC BIST (Built-In Self-Test) Circuit"
|
34 |
"Route Reinforcement for Efficient QoS Routing Based on Ant Algorithm"
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33 |
"An Acceleration Processor for Data Intensive Scientific Computing"
|
32 |
"A New Maximal Diagnosis Algorithm for Interconnect Test"
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31 |
"New Distributed Arithmetic Algorithm for Low-Power FIR Filter Implementation"
|
30 |
"A Low-Power Implementation Scheme of Interpolation FIR Filters Using Distributed Arithmetic"
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