59 |
"High-efficiency memory BISR with two serial RA stages using spare memories"
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58 |
"A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-random Logic BIST"
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57 |
"MTR-fill : A Simulated Annealing-based X-filling Technique to Reduce Test Power Dissipation for Scan-Based Designs"
|
56 |
"A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters"
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55 |
"NoC-Based SoC Test Scheduling Using Ant Colony Optimization"
|
54 |
"A New Analog-to-Digital Converter BIST Considering a Transient Zone"
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53 |
"Double component long period waveguide grating filter in sol-gel material"
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52 |
"MDSI : Signal Integrity Interconnect Fault Modeling and Testing for SoCs"
|
51 |
"Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing"
|
50 |
"Test Scheduling of NoC-Based SoCs Using Multiple Test Clocks"
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