64 |
"A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals"
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63 |
"Growth of Transparent nc-InGaO3(ZnO)2 Thin Films with Indium mol Ratios Using Solution Process"
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62 |
"An Effective Test and Diagnosis Algorithm for Dual-Port Memories"
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61 |
"A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment"
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60 |
"A New Scan Partition Scheme for Low-Power Embedded Systems"
|
59 |
"High-efficiency memory BISR with two serial RA stages using spare memories"
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58 |
"A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-random Logic BIST"
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57 |
"MTR-fill : A Simulated Annealing-based X-filling Technique to Reduce Test Power Dissipation for Scan-Based Designs"
|
56 |
"A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters"
|
55 |
"NoC-Based SoC Test Scheduling Using Ant Colony Optimization"
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