119 |
"A Delay Test Architecture for TSV with Resistive Open Defects in 3D-Stacked Memories"
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118 |
"Recovery-Enhancing Task Scheduling for Multicore Processors under NBTI Impact"
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117 |
"A New Fuse Architecture and a New Post-share Redundancy Scheme for Yield Enhancement in 3D-stacked Memories"
|
116 |
"A New Multi-site Test for System-on-Chip using MSTAR(Multi-site Star Test ARchitecture)"
|
115 |
"Interleaving Test Algorithm for Sub-threshold Leakage Current Defects in DRAM Considering the Equal Bit Line Stress"
|
114 |
"A novel test access mechanism for parallel testing of multi-core system"
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113 |
"Dynamic thermal management for 3D multicore processors under process variations"
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112 |
"A Flexible Programmable Memory BIST for Embedded Single-Port Memory and Dual-Port Memory"
|
111 |
"Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations"
|
110 |
"Efficient Multi-ste Testing using ATE Channel Sharing"
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