| 125 | 
			"Histogram-based Calibration Method for Pipeline ADCs"
			 | 
| 124 | 
			"Reduced-Code Test Method Using Sub-Histograms for Pipelined ADCs"
			 | 
| 123 | 
			"A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories"
			 | 
| 122 | 
			"A Novel Massively Parallel Testing Method using Multi-root for High Reliability"
			 | 
| 121 | 
			"A New Thermal-Aware Voltage Island Formation for 3D Many-Core Processors"
			 | 
| 120 | 
			"A BIRA for Memories with an Optimal Repair Rate Using Spare memories as an Address Mapping Table for Area Reduction"
			 | 
| 119 | 
			"A Delay Test Architecture for TSV with Resistive Open Defects in 3D-Stacked Memories"
			 | 
| 118 | 
			"Recovery-Enhancing Task Scheduling for Multicore Processors under NBTI Impact"
			 | 
| 117 | 
			"A New Fuse Architecture and a New Post-share Redundancy Scheme for Yield Enhancement in 3D-stacked Memories"
			 | 
| 116 | 
			"A New Multi-site Test for System-on-Chip using MSTAR(Multi-site Star Test ARchitecture)"
			 | 
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