144 |
"R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies"
|
143 |
"Chain-based Approach for Fast Through-Silicon-Via Coupling Delay Estimation"
|
142 |
"Hardware-Efficient Built-in Redundancy Analysis for Memory with Various Spares"
|
141 |
"Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory"
|
140 |
"A Low-cost DAC BIST Structure using a Resistor Loop"
|
139 |
"FRESH: A New Test Result Extraction Scheme for Fast TSV Tests"
|
138 |
"An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time"
|
137 |
"A Survey of Repair Analysis Methods for Memories"
|
136 |
"A New 3-D Fuse Architecture to Improve Yield of 3-D Memories"
|
135 |
"Parallelized Network on Chip-reused Test Access Mechanism for Multiple Identical Cores"
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