149 |
"Grouping-based TSV Test Architecture for Resistive Open and Bridge Defects in 3D-ICs"
|
148 |
"DRAM-based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores"
|
147 |
"DVFS-aware refresh management for 3D DRAM over processor architecture "
|
146 |
"Reconfigurable scan architecture for Test Power and Data Volume Reduction"
|
145 |
"Proof of Concept of Home IoT Connected Vehicles"
|
144 |
"R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies"
|
143 |
"Chain-based Approach for Fast Through-Silicon-Via Coupling Delay Estimation"
|
142 |
"Hardware-Efficient Built-in Redundancy Analysis for Memory with Various Spares"
|
141 |
"Low Cost Endurance Test-pattern Generation for Multi-level Cell Flash Memory"
|
140 |
"A Low-cost DAC BIST Structure using a Resistor Loop"
|
|