|
156 |
"A Statistic-based Scan Chain Reordering for Energy-Quality Scalable Scan Test "
|
|
155 |
"A debug scheme to improve the error identification in post-silicon validation"
|
|
154 |
"Fault Group Pattern Matching with Efficient Early Termination for High-Speed Redundancy Analysis"
|
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153 |
"Thermal Aware Test Scheduling for NTV Circuit "
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152 |
"Fast Built-in Redundancy Analysis Based on Sequential Spare Line Allocation"
|
|
151 |
"An Area-efficient BIRA with 1D Spare Segments"
|
|
150 |
"A novel X-filling method for capture power reduction"
|
|
149 |
"Grouping-based TSV Test Architecture for Resistive Open and Bridge Defects in 3D-ICs"
|
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148 |
"DRAM-based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores"
|
|
147 |
"DVFS-aware refresh management for 3D DRAM over processor architecture "
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