174 |
"On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug"
|
173 |
"An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process"
|
172 |
"A New Logic Topology-based Scan Chain Stitching for Test-Power Reduction"
|
171 |
"Prediction based Error Correction for GPU Reliability with Low Overhead"
|
170 |
"Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks"
|
169 |
"Fine-Grained Defect Diagnosis for CMOL FPGA Circuits"
|
168 |
"A 3-D Rotation-Based Through-Silicon Via Redundancy Architecture for Clustering Faults"
|
167 |
"Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks"
|
166 |
"Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing"
|
165 |
"GPU-Based Redundancy Analysis Using Concurrent Evaluation"
|
|