|
224 |
"TOPS: Topology-based Partial Scan for Stuck-at and Delay Testing"
|
|
223 |
"VASE: Vector Memory Using Bit-Level Address Segmentation for High-Speed Memory Testing"
|
|
222 |
"Test Cycle Reduction for TSV Test Using Streaming Scan Network on 3-D IC"
|
|
221 |
"A New Logic BIST for Complete Fault Detection Using Previous Scan-In Bit Dependency"
|
|
220 |
"TSV Built-In Self-Repair Architecture for Lifespan Reliability Enhancement of HBM"
|
|
219 |
"Multi-stage Enhanced Diagnosis with Fault Candidate Reduction"
|
|
218 |
"An Efficient Test Scheduling Method based on Dynamic Pairing"
|
|
217 |
"A Novel CNN-based Redundancy Analysis Using Parallel Solution Decision"
|
|
216 |
"A New Test Point Insertion Using Weight Adjusted Grouping"
|
|
215 |
"An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-In-Memory "
|
|
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