214

"An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-In-Memory "
Hayoung Lee, Juyong Lee, and Sungho Kang
IEEE Transactions on Very Large Scale Integration Systems
To be Published

213

"SPOT: Fast and Optimal Built-In Redundancy Analysis using Smart Potential Case Collection"
Donghyun Han, Sunghoon Kim, Dayoung Kim, and Sungho Kang
IEEE Transactions on Very Large Scale Integration Systems
To be Published

212

"A Built-In Self-Repair with Maximum Fault Collection and Fast Analysis Method for HBM"
Joonsik Yoon, Hayoung Lee, Youngki Moon, Seung Ho Shin, and Sungho Kang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
To be Published

211

"A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing"
Juyong Lee, Hayoung Lee, Sooryeong Lee, and Sungho Kang
IEEE Transactions on Very Large Scale Integration Systems
To be Published

210

"A Robust Test Architecture for Low-Power AI Accelerators"
Hayoung Lee, Juyong Lee, and Sungho Kang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
To be Published

209

"An Efficient Scan Diagnosis for Intermittent Faults using CNN with Multi-Channel Data"
Hyojoon Yun, Hyeonchan Lim, Hayoung Lee, Doohyun Yoon, Sungho Kang
IEEE Access
vol. 12 pp. 146463 - 146475, 2024.10.07

208

"A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM"
Youngki Moon, Seung Ho Shin, Seokjun Jang, Duyeon Won, and Sungho Kang
IEEE Transactions on Very Large Scale Integration Systems
To be Published

207

"An Efficient Low Power BIST for Automotive SoC with Periodic Pattern Type Selection"
Jongho Park, Sangjun Lee, Hyemin Kim, Jaeyoung Joung, Jaehyun Kim, and Sungho Kang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
To be Published

206

"Effective Parallel Redundancy Analysis Using GPU for Memory Repair"
Seung Ho Shin, Hayoung Lee, and Sungho Kang
IEEE Transactions on Very Large Scale Integration Systems
To be Published

205

"A New Pipelined Output Data Reducer of BOST for Improved Parallelism"
Sooryeong Lee, Hayoung Lee, Juyong Lee, and Sungho Kang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
To be Published