Better ATE Usages
[A-1] LS2000 ±¹»êÈ Tester program auto generation
¢º ¾ö°æ¿î, ¹Ú¼º±Ù, ±èÆÇÀç, ±èÅÂÇü, °ø¾È¿µ, ¾ç¼º·Ï, ÀÓÇýÁ¤ (»ï¼ºÀüÀÚ)
[A-2] µ¶¸³Ã¤³Î¿¡ ºñÇØ 8¹èÀÇ Å¬·° ¼Óµµ¸¦ ³ôÀÌ´Â Å×½ºÆ® ¹æ¹ý ±¸Çö
¢º ¹ÚÁøÈ¯, Stephen Kim, Á¤¼ºÅÃ, Á¤¿ë½Ä, ±è¿µÀç (Teradyne)
[A-3] Diagnostic Program Generation Tool for ATE Load Boards
¢º Bruce Kim, Venkat Kalyanaraman (University of Alabama)
[A-4] Å×½ºÆ® ÇÉ Ãà¼Ò¿¡ ÀÇÇÑ Àúºñ¿ë SoC Å×½ºÆ® ±¸Á¶
¢º ÀÌÇöºó, ±èº´Áø, ±èÁø±Ô, ±ÇÁö¿¬, ¹Ú¼ºÁÖ
[B-1] Testing Integral and Differential Non-Linearity of ADC using Servo Loop Solution
¢º Jin-Soo Ko (Teradyne)
[B-2] µðÁöÅÐ ½ÅÈ£ ÀÌ¿ëÇÑ À§»ó °íÁ¤ ·çÇÁ ÀÚü ³»Àå Å×½ºÆ® ±â¹ý
¢º ±èÀ¯ºó, ±è±âö, ±èÀÎö, ¼ÕÇö¿í, °¼ºÈ£ (¿¬¼¼´ë)
[B-3] Clock Jitter Effect for Testing Data Converters
¢º Jin-Soo Ko (Teradyne)
[B-4] È¿°úÀûÀÎ PLL Å×½ºÆ® ºñ¿ë Àý°¨ ¹æ¹ý
¢º ÀüÁØ¿ì, ¿ÁÀçö, ±èÇкÀ, ±è±âö, ±èÀ¯ºó, °¼ºÈ£ (¿¬¼¼´ë)
[C-1] Audio CODEC testing using A-weighting digital filter
¢º ¿ÀÁ¤ÈÆ (»ï¼ºÀüÀÚ)
[C-2] ºñµð¿À Ãâ·Â Å×½ºÆ®
¢º Seok Min Hyun, Kwang Suk Shin (Teradyne)
[C-3] Wafer level functional test with mDDR
¢º ¹Úº´¿í (»ï¼ºÀüÀÚ)
[C-4] An efficient Self-test scheme for Tandom Logics Interconnects
¢º Dongchul Kang, Hyomoon Cho, Dongkyun Park, Sanbock Cho (¿ï»ê´ë)
[D-1] ±ÕÀÏ Ç°Áúº¸ÁõÀ» À§ÇÑ ¾ç»ê¹æ¾È¿¡ ´ëÇÑ ¿¬±¸
¢º õº´¿Á (»ï¼ºÀüÀÚ)
[D-2] EDS contact¼º ºÒ·® °¨¼Ò¸¦ À§ÇÑ È¿°úÀûÀÎ ±â¹ý
¢º Panje Kim, Sunggeun Park, Jeongmoon Yoo, Youngsik Kim, HyeongKwon Park, Kyeongwoon Eom,
Sungrok Yang, Heyjeong Im, Manyoung Kong, Taehyeong Kim (»ï¼ºÀüÀÚ)
[D-3] ºü¸¥ °íÀå Áø´ÜÀ» À§ÇØ °íÀå Á¡¼ö¸¦ ÀÌ¿ëÇÑ °íÀå Å»¶ô ¹æ¹ý
¢º ÀÌÁÖȯ, ÀÓ¿ä¼·, °¼ºÈ£ (¿¬¼¼´ë)
[D-4] °íÀå ¼±Åà Å×À̺íÀ» »ç¿ëÇÑ ´ÙÁß °íÂø °íÀå Áø´Ü ¹æ¹ý
¢º ÀÓ¿ä¼·, ÀÌÁÖȯ, °¼ºÈ£ (¿¬¼¼´ë)
[E-1] CMOS À̹ÌÁö ¼¾¼¿¡¼ÀÇ ¾ÏÀüÈÞ ÃøÁ¤¿¡ °üÇÑ °íÂû
¢º À̱¤Èñ, ³ë½ÃÀ±, ÁÖÄ¡¼±, °½Â¿ø, ÀÓº´Çö, ÃÖÄ¡¿µ (»ï¼ºÀüÀÚ)
[E-2] Defect Modeling of CNT Interconnects for System-in-Package Allpication
¢º Bruce Kim, Gang Chen, Syed Askari Naqvi (University of Alabama)
[E-3] ÀáÀç ºÒ·® ¸ðµ¨¸µ¿¡ ÀÇÇÑ ½Å·Ú¼º ºÒ·® °¡¼Ó ¹æ¹ý
¢º J.H. Nam, Y.J. Kim, G.B. Koo, J.Y. Park, H.J. Kim, K.S. Shin, K.S. Kang, S.Kang (»ï¼ºÀüÀÚ)
[E-4] SRAM ¼¿ °£ÀÇ AC Ä¿Çøµ °íÀåÀÇ ÇØ¼®
¢º ¹èÁ¾¼±, ¹é»óÇö (ÇѾç´ë)
[F-1] ÆÐÅÏ ÁöÇâ ÇÁ·Î±×·¥À» ÀÌ¿ëÇÑ Å×½ºÆ® ½Ã°£ °¨¼Ò
¢º ¿À°ÈÆ, ÀÌ¿ëÈ, ÀÌ¸í±¸ (Teradyne)
[F-2] Åë°èÀû ¹æ¹ý¿¡ ±Ù°ÅÇÑ SCAN Failure Analysis
¢º ¿À±æ±Ù, ¼»ó³², ÀåÁ¦¿, Çѵ¿°ü, ȲÀçö, À̽ÂÇõ, Á¤¿µÅÃ, Ãֿ켺 (»ï¼ºÀüÀÚ)
[F-3] È¿°úÀûÀÎ AMBA±â¹Ý SoC Å×½ºÆ®¸¦ À§ÇÑ AHB/PCI ¹ö½º ºê¸®Áö Àç»ç¿ë ±â¼ú
¢º ÇÑÁÖÈñ, ¼ÛÀçÈÆ, Á¶»ó¿í, ¹Ú¼ºÁÖ (ÇѾç´ë)
[F-4] Scan-Chain°ú IEEE 1500 ·¡ÆÛ¸¦ ÀÌ¿ëÇÑ SoC Áö¿¬ °íÀå Å×½ºÆ®
¢º ±èÁø±Ô, ÀÌÇöºó, ÀÌÁؼ·, Á¤ÅÂÁø, ¹Ú¼ºÁÖ (ÇѾç´ë)
[G-1] SI/PI SimulationÀ» ÀÌ¿ëÇÑ Test Board ¼³°è
¢º ³²½Â±â, ½Å¿¬¼÷, ¼ºÁ¤¿ì, ±èżö, ±è¼ºÇö, ±èÀºÁ¤, Á¶¼ø¿µ, ÀÓ¿µ¼ø, ±è¿µºÎ (»ï¼ºÀüÀÚ)
[G-2] Signal Integrity¸¦ °í·ÁÇÑ SoC ¿¬°á¼± Å×½ºÆ®¿ë ´ÙÁß ÃµÀÌ ÆÐÅÏ »ý¼º±â
¢º ±è¿ëÁØ, ¾ç¸íÈÆ, ¹Ú¿µ±Ô, ÀÌ´ë¿, À±ÇöÁØ, °¼ºÈ£ (¿¬¼¼´ë)
[G-3] °áÇÕ Á¤Àü¿ë·®À» ÀÌ¿ëÇÑ Crosstalk Noise ÃßÁ¤ ¸ðµ¨
¢º ±èÅÂÁø, Á¶ÇüÁØ, Àü¼ºÈÆ, °¼ºÈ£ (¿¬¼¼´ë)
[G-4] NBTU°¡ ¹ß»ýÇÑ SRAM Cell ÀÇ Ground Bounce ¿µÇ⠺м®
¢º ÃÖÅ¿ø, ¹é»óÇö (ÇѾç´ë)
[G-5] AC NOISE¿¡ ÀÇÇÑ Buard Band ¿µÇ⼺ ¿¬±¸
¢º ÁøÁ¾ÁÖ, ±è¿µ°¢, À̱¸È¯, Á¶º´È¯, ±èº´À± (»ï¼ºÀüÀÚ)
[H-1] Â÷¼¼´ë ¸Þ¸ð¸® µðÀÚÀÎÀ» À§ÇÑ Fine Pich Link ±¸Á¶ÀÇ ·¹ÀÌÀú Fuse ProcessingÀÇ Çâ»ó
¢º Joohan Lee, Joseph J. Griffiths and James Cordingley (GSI)
[H-2] Advances in Laser Technologies for Semoconductor MEmory Yield and Rapair Applications
¢º Andy E. Hooper, Robert Hainsey and Paul Kirby (Electro-Sceitific Industries)
[H-3] ASV(Adaptive Supply Voltage)¸¦ Àû¿ëÇÑ ¼öÀ²°³¼± Algorithm Á¦¾È
¢º ±èÁؼº, ·ùÁ¤¼ö, ¿ÀÇö¼·, Àü¼ø±Ç, ÀÌÁ¶ÇÊ, ¹ÚÇö¼ö, ÃÖº´¿í, ¹è¿ëÅ (»ï¼ºÀüÀÚ)
[H-4] ³»Àå ¸Þ¸ð¸® ÀÚü º¹±¸¸¦ À§ÇÑ Àç¹èÄ¡ È¥ÇÕ ±â¹ý
¢º ¼ÛÁÂÈñ, ½ÉÀº¼º, Àå ÈÆ (¼þ½Ç´ë)
[I-1] IEEE Std.1500 ÀÎÅÍÆäÀ̽º¸¦ »ç¿ëÇÑ Programmable MBIST ±¸Á¶
¢º ¹Ú±âÇö, ±è±Ù¹è, ±èÀÏ¿õ, °ÀϱÇ, ¾çµ¿ÈÆ, °¼ºÈ£ (¿¬¼¼´ë)
[I-2] °áÇÔ ÁÖÀÔ ±â¹Ý °íÁ¤ °ËÃâÀ» À§ÇÑ ÇÁ·Î±×·¥ °¡´ÉÇÑ BIST ±¸Á¶
¢º ÀÌâ¿í, È«¿ø±â, Àå ÈÆ (¼þ½Ç´ë)
[I-3] °í¼Ó ¸Þ¸ð¸® Å×½ºÆ®¸¦ À§ÇÑ ÆÄÀÌÇÁ¶óÀÎ ALPG
¢º À±ÇöÁØ, ¾ç¸íÈÆ, ±è¿ëÁØ, ¹Ú¿µ±Ô, ÀÌ´ë¿, °¼ºÈ£ (¿¬¼¼´ë)
[J-1] Hot temperature Test½Ã ÃÖÀûÀÇ ¿¹¿½Ã°£ ÃøÁ¤¿¡ °üÇÑ ¿¬±¸
¢º ¾çµ¿½Å (»ï¼ºÀüÀÚ)
[J-2] ¸®´ø´ø½Ã ÆäÀÏ ¸ðµå ¼³°è ¹× Å×½ºÆ® ¹æ¹ý
¢º Àü¼ø±Ù, Ȳ¼¼Çö, Ç¥¼®¼ö (»ï¼ºÀüÀÚ)
[J-3] ACO¸¦ ÀÌ¿ëÇÑ ÀúÀü·Â ¸Þ¸ð¸® ECC ȸ·Î ±¸¼º ¹æ¾È
¢º ÀÌ´ë¿, ¾ç¸íÈÆ, ±è¿ëÁØ, ¹Ú¿µ±Ô, À±ÇöÁØ, °¼ºÈ£ (¿¬¼¼´ë)
[K-1] ¹ÝµµÃ¼ WaferÀÇ Fail ¿µ¿ª ºÐ¼®À» ÅëÇÑ ÀÌ»ó Wafer °ËÃâ
¢º °Áß¿í, ±èÈ£¹Î, Á¤±¤¿õ, ±è¿µºÎ (»ï¼ºÀüÀÚ)
[K-2] Decoupling Design through Parasitic Elements Analysis for Test Boards
¢º ¼Û±âÀç (»ï¼ºÀüÀÚ)
[K-3] ½Ç½Ã°£ ALU ¿¡·¯ °ËÃâÀÇ ¿¡·¯ ÀüÆÄ ¹®Á¦ÇذáÀ» À§ÇÑ È¿°úÀûÀÎ Berger Code Prediction Çϵå¿þ¾î ±¸Á¶
¢º ±è±Ù¹è, ±èÀÏ¿õ, °ÀϱÇ, ¹Ú±âÇö, ¾çµ¿ÈÆ, °¼ºÈ£ (¿¬¼¼´ë)
[L-1] NACÀ» ÀÌ¿ëÇÑ ¿þÀÌÆÛ Å×½ºÆ®¿ë ÇÁ·ÎºêÄ«µå Àü±âÀû Ư¼º ºÐ¼®
¢º ±è±Ô¿, º¯¾ðÁ¶, °±â»ó, Àü¿µÇö, °ø¹è¼± (»ï¼ºÀüÀÚ)
[L-2] Wafer Æò°¡ ÀÚµ¿È algorithm system °³¹ß
¢º ·ùÁ¤¼ö, ¹ÎÇüº¹, ±èÁؼº, ±èº´À± (»ï¼ºÀüÀÚ)
[L-3] Probe Card Checker °³¹ß
¢º ±èÇö½Ä, ±èÇöÁÖ, ÀåÁ¾¹®, ¾Èº´¿í, À嵿½Ä, ±è¿µ½Ä, ±èÀ±±â, À¯Á¤¹®, ¹ÚÇü±Ç (»ï¼ºÀüÀÚ)