½ºÄµ ȯ°æ¿¡¼­ °£Á¢ À¯Ãß ¾Ë°í¸®ÁòÀ» ÀÌ¿ëÇÑ °æ·Î Áö¿¬ °íÀå °Ë»ç ÀÔ·Â »ý¼º±â Delay Fault Test Pattern Generator Using Indirect Implication Algorithms in Scan Environment (¿ä¾à) - ȸ·Î°¡ º¹ÀâÇØÁö°í, °í¼ÓÈ­µÇ¸é¼­ ȸ·ÎÀÇ µ¿ÀÛ¿¡ ´ëÇÑ °Ë»ç »Ó ¾Æ´Ï¶ó, ȸ·Î°¡ ¿øÇÏ´Â ½Ã°£ ³» ¿¡ µ¿ÀÛÇÔÀ» º¸ÀåÇÏ´Â Áö¿¬°Ë»çÀÇ Á߿伺ÀÌ Á¡Á¡ Ä¿Áö°í ÀÖ´Ù. º» ³í¹®¿¡¼­´Â ÁÖ»çȯ°æÀ» »ç¿ëÇÏ´Â ¼øÂ÷ ȸ·Î¿¡¼­ÀÇ °æ·Î Áö¿¬ °íÀåÀ» À§ÇÑ Å×½ºÆ® ÆÐÅÏ »ý¼º °úÁ¤À» È¿À²ÀûÀ¸·Î ¼öÇàÇÒ ¼ö ÀÖµµ·Ï ºü¸¥ ½Ã°£¿¡ °£Á¢ À¯Ã߸¦ ¼öÇàÇÒ ¼ö ÀÖ´Â ¾Ë°í¸®ÁòÀ» Á¦¾ÈÇÑ´Ù ±¸Á¶ÀûÀ¸·Î ¹ß»ý °¡´ÉÇÑ Á¤Àû ÇнÀ °úÁ¤Àº Å×½ºÆ® ÆÐ ÅÏ »ý¼º °úÁ¤ ÁßÀÇ ¼±Çà ó¸® ´Ü°è¿¡¼­ °¢°¢ÀÇ °ÔÀÌÆ®¿¡ Á¤Àû ÇнÀÀÌ ¹ß»ýÇÒ ¼ö ÀÖ´Â °æ¿ì¸¦ ºÐ¼®ÇÏ¿© ±× Á¤º¸¸¦ °¢°¢ÀÇ °ÔÀÌÆ®¿¡ ´ëÇØ ÀúÀåÇÏ°í ÀÖ´Ù°¡ ¾Ë°í¸®ÁòÀ» ÀÌ¿ëÇÑ Å×½ºÆ® ÆÐÅÏ »ý¼º °úÁ¤ Áß Á¶°Ç¿¡ ¸¸Á·ÇÏ´Â °æ¿ì¿¡ À¯ÃßµÉ ¼ö ÀÖ´Â °ªÀ» ¹Ù·Î ÇÒ´çÇÏ°Ô µÈ´Ù. º» ³í¹®¿¡¼­´Â À̸¦ Áö¿¬°íÀå °ËÃâ¿¡ ¸Âµµ·Ï ¼öÁ¤ÇÏ¿© ÀÌ¿ëÇÏ¿´´Ù. ȸ·Î ³»¿¡ ¸î¸î ÁÖÀԷ¿¡¼­ ³ª¿Â ½ÅÈ£¼±À» ¸ðµÎ Æ÷°ýÇÏ´Â ºÐÇÒÁöÁ¡ÀÌ Á¸ÀçÇϸé, ÀÌ ÁöÁ¡À» Áö³ª´Â °æ·Î µé Áß¿¡ ±× ÀÌÀü, ȤÀº ÀÌÈÄÀÇ °æ·Î°¡ µ¿ÀÏÇÑ °æ·ÎµéÀº ºÐÇÒÁöÁ¡¿¡ ÀÇÇØ ºÐÇÒµÈ ÀÔ·ÂÀÇ ºÎºÐµéÀÌ °°Àº ÀԷ°ªÀ» ÇÊ¿ä·Î ÇÔÀ» ¿¹»óÇÒ ¼ö ÀÖ´Ù. º» ³í¹®¿¡¼­´Â °æ·Î Áö¿¬ °íÀå °ËÃâ¿¡¼­ À¯¿ëÇÏ°Ô »ç¿ëµÉ ¼ö ÀÖ ´Â ÀÌ·¯ÇÑ È¸·ÎºÐÇÒÀ» »ç¿ëÇÏ¿© º¸´Ù È¿À²ÀûÀ¸·Î Å×½ºÆ® ÀÔ·ÂÀ» »ý¼ºÇÏ¿´´Ù. ¸¶Áö¸·À¸·Î, ÀÌ µÎ °¡Áö ¾Ë°í¸®ÁòÀ» Àû¿ëÇÑ È¿À²ÀûÀÎ °æ·Î Áö¿¬ °íÀå Å×½ºÆ® ÀÔ·Â »ý¼º±â¸¦ °³¹ßÇÏ¿´À¸ ¸ç, ¾Ë°í¸®ÁòÀÇ È¿¿ë¼ºÀ» ½ÇÇèÀ» ÅëÇÏ¿© ÀÔÁõÇÏ¿´´Ù. (ABSTRACT) - The more complex and large digital circuits become, the more important delay test becomes which guarantees that circuits operate in time. In this paper, the proposed algorithm is developed, which enable the fast indirect implication for efficient test pattern generation in sequential circuits of standard scan environment. Static learning algorithm enables application of a new implication value using contrapositive proposition. The static learning procedure found structurally, analyzes the gate structure in the preprocessing phase and store the information of learning occurrence so that it can be used in the test pattern generation procedure if it satisfies the implication condition. If there exists a signal line which include all paths from some particular primary inputs, it is a partitioning point. If paths passing that point have the same partial path from primary input to the signal or from the signal to primary output, they will need the same primary input values which separated by the partitioning point. In this paper test pattern generation can be more effective by using this partitioning technique. Finally, an efficient delay fault test pattern generator using indirect implication is developed and the effectiveness of these algorithms is demonstrated by experiments.