순차 회로의 지연 고장 검출을 위한 새로운 스캔 설계
New Scan Design for Delay Fault Testing of Sequential Circuit


(Abstract) Delay testing has become highlighted in the field of digital circuits as the 
speed and the density of the circuits improve greatly. However, delay faults in 
sequential circuits cannot be detected easily due to the existence of state registers. To
 overcome this difficulty a new scan flip-flop is devised which can be used for both 
stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied 
to both the existing functional justification method and the newly-developed reverse 
functional justification method which uses scan flip-flops as storing the second test 
patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark
 circuits show that the number of testable paths can be increased by about 10% on the
 average.